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Showing posts from September, 2018

MODULE 1

Presentation download link here: https://drive.google.com/file/d/1lwT34XK9nundqq6okpMcZFp82Jb9YKso/view?usp=sharing

VerilogHDL_syllabus

VERILOG HDL B.E., V Semester, Electronics & Communication Engineering [As per Choice Based Credit System (CBCS) Scheme] Course Code 17EC53                                                                                   CIE Marks 40 Number of Lecture Hours/Week 04                                                     ...